Monolithically integrated solar cell microarray and fabrication method

ABSTRACT

A monolithically integrated solar cell microarray includes an isolation layer or multiple isolation layers between a substrate and a solar cell layer, and a trench in the solar cell layer that exposes the isolation layer. Together the isolation layer and trench define solar cells that are spaced apart and electrically isolated on the monolithic substrate. The solar cells are scaled to provide a desired current. Base contacts and integral emitter contact/interconnects connect a number of the scaled solar cells in series to sum their voltages to supply a desired output voltage and current. The trench and integral emitter contact/interconnects are formed using photolithographic etching and liftoff processes, respectively, which are much quicker and less expensive than the conventional dicing and soldering processes.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to solar cell microarrays, andmore specifically to a monolithically integrated solar cell microarrayand a method for photolithographically isolating the individual solarcells and defining series interconnects therebetween.

2. Description of the Related Art

Microarrays which may include a hundred or more solar cells are used toprovide electrical power for a variety of applications such asspacecraft. Existing microarrays are formed by growing p and n typesemiconductor layers such as gallium-arsenide (GaAs) on a germanium (Ge)wafer to form an active p/n junction. The wafer is cut or "diced" intounit sized solar cells. Dicing limits the solar cells to rectangularshapes, damages the solar cells and takes approximately 30 minutes permicroarray.

Irradiating the microarray with light causes each solar cell to producea voltage potential and a current. The discrete solar cells areinterconnected in series/parallel combinations to sum the individualcell voltages and currents, respectively, to supply a desired arrayvoltage and current. The solder interconnects increase the microarray'sweight, obscure the solar cells' active area thereby reducingefficiency, increase manufacturing costs and provide inferiorelectro-mechanical interconnects. Furthermore, the cell-to-cell spacingmust be at least 100 microns.

FIG. 1 is a sectional view of a portion of a known solar cell microarray10 bonded to a carrier 12. The microarray 10 includes a plurality ofdiscrete single junction GaAs solar cells 14 formed on respective Gesubstrates 16. Single and multi-junction GaAs cells produce potentialsof approximately 1 V and 2.5 V, respectively, and supply a cell currentof approximately 30 milliamperes/cm² and 16 milliamperes/cm²,respectively The solar cells use electrically conductive interconnects18 in a parallel/series circuit to produce a power supply with a desiredvoltage and current for a given application.

Each solar cell 14 includes an n-type GaAs base layer 20, suitably 5microns thick, grown on substrate 16. A p-type GaAs emitter layer 22,suitably 0.5 micron thick, is grown on the base layer 20 such that theirinterface defines a p/n junction 24 having a band gap of approximately1.4 eV. The substrates 16 are 200 microns Ge single crystal substrateswhich are suitable for Metalorganic Chemical Vapor Deposition (MOCVD) ofGaAs solar cells. The Ge substrates match the thermal and latticeproperties of the base and emitter layers 20 and 22, respectively. Thismatch is important to avoid cracks in the solar cells 14.

A p-type AlGaAs window layer 26, suitably 0.05 microns thick, is grownon emitter layer 22. The window layer 26 passivates the surface 28 ofthe emitter layer 22 to protect the solar cell from contamination and toincrease the conversion efficiency. The window layer 26 has a band gapin excess of 2 eV so that incident light is transmitted through thewindow to the solar cell 14.

A base contact region 30 is formed through the window and emitter layersinto base layer 20. A base contact 32, suitably a AuGeNiAg alloy, isformed in contact region 30 to adhere to the n-type GaAs base layer 20.In most known microarrays, the base contact 32 is formed on the backsideof the solar cell as parallel grid lines. A p-type GaAs emitter contactpad 34 or "cap" layer is formed on window layer 26 in electricalcommunication with the emitter layer 22. An emitter contact 36, suitablya AuZnAg alloy, is formed on the p-type contact pad 34. The base andemitter contacts are formed from different metal alloys because theymust adhere to n and p-type GaAs, respectively.

Light incident on the front or active surface 37 of the microarraypasses through the window layer 26 and is partially absorbed in theemitter and base layers 22 and 20, respectively. The microarray's activesurface 37 and back or "shadowed" surface 38 are coated with anantireflection (AR) coating 39 that enhances light transmission, therebyincreasing the array's power efficiency. The absorption of light causesliberation of charge carriers including electrons and holes in theregion of the p/n junction 24, which migrate towards the top surface 28of the emitter layer and the bottom surface 40 of the base layer,depending upon their polarity. The opposite charge carriers arecollected at the base contact 32 and emitter contact 36. This generatesa potential of approximately 1 V across the solar cell 14 and supplies acurrent of 30 milliamperes/cm².

The microarray 10 is manufactured generically, without interconnects 18,so that the manufacturer or user can configure the solar cells 14 for aparticular application. The generic microarray is fabricated by firstgrowing 200 microns thick Ge wafer. Ge wafers are limited to muchsmaller sizes than Si wafers, typically 10.2 cm in diameter, and aremore expensive than Si. However, even though much research has been doneto grow GaAs solar cells directly on Si substrates, those efforts havelargely failed. The mismatch in lattice and thermal properties of Si andGaAs results in cracks in the solar cells.

The base, emitter, window, and cap layers are grown with an epitaxialprocess onto the wafer. The structure is then chemically etched todefine all of the base contact regions 30 in parallel. Similarly the caplayer is etched to define all of the emitter contact pads 34 inparallel. The discrete base and emitter contacts 32 and 34 are formed inrespective lift-off metalization steps.

The wafer is then sawed or diced to define the discrete solar cells andassociated substrates. Dicing is a serial process that is limited tolinear cuts of the wafer. As a result, dicing an entire wafer is a veryslow and expensive process, taking up to about 30 minutes. The processcan also damage the edge of the solar cells and reduce their output.Furthermore, the solar cells are limited to rectangular shapes. In knownmicroarrays, each of the solar cells conforms to a reference size andshape. The discrete solar cells 14 and their affixed substrates 16 arebonded to the carrier 12 in physical and electrical isolation from eachother.

The solar cells 14 are connected together by manually solderinginterconnects 18 between contacts on adjacent solar cells along thesurface of carrier 12. The connections depend upon the power supplyspecifications: supply voltage and supply current. These values arespecified as integer multiples of the cell voltage and current so that anumber of cells can be connected in parallel to provide the desiredsupply current and connected in series to provide the supply voltage.For example, a 5 v supply would be provided by soldering five solarcells in series. The completed structure (microarray and carrier) isthen bonded to the spacecraft's solar panel.

Manual soldering is a slow, and thus expensive, serial process, takingbetween 1/2 and 2 hours per microarray, depending upon the number ofcontacts. The contacts between the interconnects and base and emittercontacts may be weak and break. Furthermore, the soldered interconnects18 have a line width of approximately 125 microns which obscure asignificant portion of the incident light and increases the overallweight of the microarray.

A solar cell of this general type is disclosed in U.S. Pat. No.5,330,585 "GaAS/AlGaAs Photocell including Environmentally Sealed OhmicContact Grid Interface and Method of Fabricating the Cell," assigned toHughes Aircraft Company, assignee of the present invention.

SUMMARY OF THE INVENTION

The present invention seeks to provide a light weight and efficientsolar cell microarray and a cost effective method for manufacturing themicroarray.

This is accomplished by forming base and emitter semiconductor layers ofopposite conductivity types on a monolithic substrate. An isolationlayer formed between the substrate and the base layer, together with atrench formed in the base and emitter layers that exposes the isolationlayer, define solar cells that are spaced apart and electricallyisolated from the monolithic substrate. The trench isphotolithographically etched into the microarray, and thus can be formedmuch quicker and with less damage to the cells than conventional dicingtechniques. The etch is controlled to scale the individual solar cellsto produce the desired output current, thus eliminating the prior needto connect the cells in parallel. Base contacts and integral emittercontact/interconnects are formed using a photolithographic liftoffprocess to connect a number of the scaled solar cells in series to sumtheir voltages and thereby supply the desired output voltage andcurrent. The photolithographic liftoff process is much quicker and lessexpensive than known soldering methods and provides substantiallynarrower line widths, reducing obscuration and weight.

For a better understanding of the invention, and to show how the samemay be carried into effect, reference will now be made, by way ofexample, to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1, described above, is a sectional view of a portion of a knownmicroarray;

FIG. 2 is a sectional view of a portion of a monolithically integratedmicroarray along section line 2--2 in FIG. 3 in accordance with thepresent invention;

FIG. 3 is a plan view of the microarray in FIG. 2;

FIGS. 4a through 4f are sectional views illustrating sequential steps inthe fabrication of the microarray in FIG. 2;

FIG. 5 is a plan view of an alternate embodiment of the microarrayillustrating non-rectangular solar cells; and

FIG. 6 is a sectional view of a multijunction monolithically integratedmicroarray formed in accordance with the invention.

DETAILED DESCRIPTION OF THE INVENTION

In the present invention, a monolithically integrated solar cellmicroarray is designed and fabricated in accordance with power supplyspecifications for a particular application. The solar cell microarrayis fabricated on a single monolithic substrate by providing an isolationlayer between the substrate and the solar cell base and emitter layers,and by etching those layers to expose the isolation layer. Takentogether, the isolation layer and etch define the electrically isolatedsolar cells. The solar cells are thus defined simultaneously, whichgreatly reduces manufacturing time and cost. Furthermore, the etchingprocess allows arbitrarily shaped and sized solar cells and does notdamage the solar cells. The parallel interconnections required in theknown microarrays to sum the cell currents are eliminated by directlyscaling the solar cells' active areas to provide the desired supplycurrent.

Because the solar cells are defined without sawing the wafer, the seriesinterconnects can be formed using a photolithographic lift-off oretching process. This has several beneficial results. First, theinterconnects can be formed in parallel at the same time as the emittercontacts. This adds no time to the fabrication of the microarray andsaves 1/2 to 2 hours compared to the existing method. Second, the linewidth of the interconnects is reduced from 125 microns to approximately5 microns. This reduces obscuration by 10-15% and reduces the weight ofthe metallization by a factor of approximately twenty-five. Third,integrating the interconnects with the emitter contacts improves thequality of the contact.

FIG. 2 is a sectional view of a portion of a monolithically integratedsolar cell microarray 50 in accordance with the present invention.Microarray 50 includes a plurality of solar cells 52 formed on amonolithic substrate 54. The invention is described in conjunction withsingle junction GaAs solar cells 52 and a 200 microns thick n-type Gesubstrate 54, but is applicable to multijunction solar cells and is notlimited to the specific conductivities or materials shown. For example,the solar cells can be formed from InGaAsP, InGaAs, or InP. Furthermore,the invention allows larger GaAs microarrays to be fabricated on a largeSi substrate.

The microarray 50 includes n and p-type GaAs base and emitter layers 56and 58, respectively, that define a p/n junction 60 having a band gap ofapproximately 1.4 eV at their interface. The base and emitter layers aresuitably 5 microns and 0.5 micron thick, respectively. A patternedtrench 62 in the base and emitter layers and an isolation layer 64between the base layer 56 and the substrate 54 together define theindividual solar cells 52.

The patterned trench 62 exposes the isolation layer 64, thereby spacingthe solar cells 52 apart by approximately 50 microns. The trench ispreferably formed to expose the top surface of isolation layer 64.Alternately, the trench can be formed into or through the isolationlayer 64 into the substrate 54. The trench 62 can be patterned so thatthe solar cells have the conventional rectangular shape, or othernon-rectangular shapes such as triangles. Furthermore the trench can bepatterned to scale the sizes of the solar cells by varying amounts toproduce the desired supply currents. This eliminates the need to connectmultiple cells in parallel, thereby reducing the weight of themicroarray and the cost of production.

The isolation layer 64 electrically isolates the individual solar cells52 from the substrate 54, thereby breaking the current leakage pathbetween the cells through the substrate. This electrically isolates thesolar cells 52 from each other. The isolation layer 64 is preferably asemiconductor material having the opposite conductivity type of thesubstrate 54 and base layer 56 and doped to have a high resistance. Inthe embodiment discussed, isolation layer 64 is suitably a 1 micronlayer of p-type AlGaAs doped to have a band gap of approximately 2 eV.Alternately, other III-V materials could be used to form the isolationlayer. Further, multiple isolation layers such as a p-n-p composite mayalso be used to reduce the electrical conductivity between the solarcells and the substrate.

The semiconductor material selected for the isolation layer 64 must alsohave thermal and lattice constant properties that are compatible withthose of the substrate 54 and base layer 56. The material can beselected to have properties between those of GaAs solar cells and Gesubstrates.

A p-type AlGaAs window layer 66, suitably 0.05 microns thick, passivatesemitter layer 58. The window layer 66 is doped to have a band gap inexcess of 2 eV so that incident light is transmitted through the windowto the solar cells 52. A base contact region 68 is formed through thewindow and emitter layers into base layer 56. A base contact 70,suitably a AuGeNiAg alloy, is formed in contact region 68 to adhere tothe n-type GaAs base layer 56. A p-type GaAs emitter contact pad 72 or"cap" layer is formed on top of window layer 66 in electricalcommunication with the emitter layer 58. An integrated emittercontact/interconnect 74, suitably a AuZnAg alloy, connects the p-typecontact pad 72 of one cell 52 to the base contact 70 of another solarcell 52. The interconnect portion of contact/interconnect 74 has a linewidth of at most 25 microns and preferably approximately 5 microns,which reduces obscuration by 5-10% and reduces the overall metallizationweight by a factor of approximately twenty-five.

The base and emitter/interconnect contacts are preferably formed fromdifferent metal alloys to improve their adherence to n and p-type GaAsbase and emitter layers, respectively. Alternately, the interconnectcould be formed integrally with the base contact instead of the emittercontact. Furthermore, the emitter and base contacts and interconnect canbe formed as a single integral contact. Integration of the contactsimproves their quality and simplifies the manufacturing process.

Light incident on the front or active surface 76 of the microarraypasses through the window layer 66 and is partially absorbed in theemitter and base layers 56 and 58, respectively. The microarray's activesurface 76, back or "shadowed" surface 78, and inner walls of the basecontact region 68 and trench 62 are coated with an antireflection (AR)coating 80 such as tantalum pentoxide (Ta₂ O₅) and aluminum oxide (Al₂O₃) that enhances light transmission, thereby increasing the array'spower efficiency, and prevents shunting by the interconnecting topmetals. The absorption of light causes a liberation of charge carriers,including electrons and holes, in the region of the p/n junction 60,which migrate towards the top surface 82 of the emitter layer and thebottom surface 84 of the base layer, depending upon their polarities.The opposite charge carriers are collected at the base contact 70 andemitter contact 74. This generates a potential of approximately 1 Vacross the solar cell 52 and supplies a current in the range of 1 to 5milliamps, depending upon the size of the p/n junction's active area.The light penetrates only approximately 3 microns into the solar cell,and thus the p/n junction formed between the isolation layer 64 andsubstrate 54 is inactive.

As shown in FIG. 3, the microarray 50 is designed and fabricated toprovide one or more power supplies with desired voltage and currentlevels for a given application. The trench 62 is patterned to scale thesolar cells relative to a reference cell, typically 1.2 cm by 0.3 cm, toprovide the desired current levels. The emitter contact/interconnects 74connect the solar cells into series strings to sum their voltages andproduce the desired voltage levels.

In the particular example shown, microarray 50 provides three supplies:nominally an 8 V 3 milliamp supply, a 12 V 2 milliamp supply, and a 24 V1 milliamp supply. The base contact of the first solar cell 52 in eachstring is connected to an external ground and the emitter contact 74 ofthe last solar cell 52 in each string is connected to an externalvoltage terminal 86. Alternately, the trench 62 could be patterned toprovide unit sized solar cells which are then connected in parallel toprovide the desired current levels. However, because the microarray isdesigned for a specific application, this would be inefficient.

As shown in FIGS. 4a through 4f, the monolithically integrated solarcell microarray 50 of FIGS. 2 and 3 is fabricated entirely with aphotolithographic process which does not require sawing the wafer toisolate the individual cells or manually soldering the electricallyconductive interconnects. Furthermore, the solar cells and interconnectsare fabricated to provide a power supply(s) for a specific application.In FIG. 4a, the Ge wafer 54 has been grown and the isolation, base,emitter, window, and cap layers 64, 56, 58, 66, and 72, respectively,have been epitaxially formed thereon with thickness of 200 microns, 1micron, 5 microns, 0.5 micron, 0.05 micron and 0.5 micron, respectively.

In FIG. 4b, base contact regions 68 have been formed through the cap,window, and emitter layers and into the base layer 56. This ispreferably done by masking the active surface 76 of the microarray 50and then chemically etching the exposed portions to a depth ofapproximately 3 to 4 microns. In FIG. 4c, trench 62 has been patternedthrough the cap, window, emitter, and base layers to expose theisolation layer 64. This is preferably done by masking the activesurface 76 of the microarray 50 and then chemically etching the exposedportions to a depth of approximately 6.5 microns. In FIG. 4d, the caplayer has been etched with a similar process to defined the emittercontact pad 72. The ordering of the fabrication steps shown in FIGS. 4bthrough 4d can be interchanged.

In FIG. 4e the AR coating 80 has been formed over both the microarray'sshadowed and active surfaces. The active surface is masked so that theAR coating does not cover the bottom of base contact regions 68 andemitter contact pad 72. In FIG. 4f the base contacts 70 and emittercontact/interconnect 74 have been deposited on the active surface 76 toconfigure the solar cells to provide the desired power supplies. Thebase contacts and emitter contact/interconnects are fabricated inrespective photolithographic liftoff steps to accommodate the differentmetal alloys. Each liftoff step includes forming a photoresist layerover the microarray, etching the photoresist to expose the base contactregion or emitter contact pad, forming the appropriate metallizationlayer over the patterned photoresist so that it adheres to the baselayer or the emitter contact pad, and lifting off the photoresist toremove the remaining metallization. Alternately, the metal contacts canbe formed by etching.

The photolithographic process used to fabricate the microarray hasseveral advantages over the known fabrication techniques. The trenchetch is accomplished in a single parallel step which can be much quickerand cheaper than conventional dicing. The parallel trench etch does notdamage the solar cells and reduces the spacing between cells, whichimproves the microarray's overall efficiency. Furthermore, the solarcells are not limited to rectangular shapes. The photolithographicliftoff process forms the interconnects at the same time and integralwith the emitter contacts. This reduces fabrication time and cost andimproves the quality of the contacts. The photolithographically definedinterconnects have a much narrow line width than prior solderinterconnects, and thus reduce light obscuration and weight.

FIG. 5 shows an alternate embodiment of a microarray 88, in which thespacecraft requires a triangularly shaped microarray. In thisembodiment, the trench mask is designed to provide a triangularlypatterned trench 90 that defines triangularly shaped solar cells 92.

FIG. 6 is a sectional view of a microarray 94 that includesmultijunction solar cells 96 formed on a monolithic substrate 98. Anisolation layer 100, suitably p-type AlGaAs, separates the solar cells96 from the substrate 98. Alternately, the isolation layer could be acomposite p-n-p type layer. The multijunction solar cell 96 includesthree pair of base-emitter layers 102, 104, and 106 formed from Ge,GaAs, and GaInP₂ with band gaps of approximately 0.6, 1.4, and 1.9 eV,respectively. A window layer 108, emitter contact pad 110 and AR coating112 are formed similarly to the single junction solar cells. A basecontact region 114 is etched through to the base layer in the bottommost pair 102 and the trench etch 116 is etched through the three layerpairs to expose the isolation layer 100. Base contacts 118 and emittercontact/interconnects 120 are formed in and on the base contact region114 and emitter contact pad 110, respectively. Light incident on themicroarray penetrates to all three p/n junctions, thereby producing apotential of approximately 2.5 V.

While several illustrative embodiments of the invention have been shownand described, numerous variations and alternate embodiment will occurto those skilled in the art. Such variations and alternate embodimentsare contemplated, and can be made without departing from the spirit andscope of the invention as defined in the appended claims.

We claim:
 1. A monolithically integrated solar cell microarray,comprising:a monolithic single-crystal semiconductor substrate; anisolation layer on said substrate, said isolation layer having latticeproperties that are compatible with those of the single-crystalsemiconductor substrate; and a plurality of semiconductor solar cellscomprising III-V materials on said isolation layer and spaced apart fromeach other, said isolation layer having a band gap that electricallyisolates the solar cells from the semiconductor substrate and from eachother.
 2. The microarray of claim 1, wherein said solar cells aregallium-arsenide (GaAs) and the substrate is germanium (Ge).
 3. Themicroarray of claim 2, wherein said germanium substrate has a band gapof approximately 0.6 ev, said isolation layer comprising a III-Vmaterial whose band gap isolates the solar cells from the substrate. 4.The microarray of claim 1, wherein said solar cells have anon-rectangular shape.
 5. The microarray of claim 1 wherein said solarcells have respective active areas, said solar cells generating cellvoltages and supplying cell currents in proportion to the sizes of theirrespective active areas in response to incident light, a set of saidsolar cells being connected in series to sum their voltages to providean array voltage at an output and having their active areas scaled tosupply scaled cell currents at a selected array current level at saidoutput.
 6. The microarray of claim 5, wherein said solar cells haveactive surfaces facing away from said substrate, each solar cell in saidset comprising:a semiconductor base layer on said isolation layer andscaled with respect to said reference area; a semiconductor emitterlayer on said base layer and scaled with respect to said reference area,an interface between said base and emitter layers forming a p/n junctionwith the scaled active area; a base contact on the active surface, saidbase contact extending through said emitter layer to said base layer;and an integral emitter contact/interconnect on the active surface inelectrical communication with said emitter layer and with said basecontact on another one of said solar cells in said set, said p/njunction establishing the cell voltage and scaled cell current betweensaid base and emitter contacts in response to incident light on thecell's active surface.
 7. The microarray of claim 6, wherein saidisolation layer has the opposite conductivity of said substrate and saidbase layer.
 8. The microarray of claim 6, wherein said emittercontact/interconnect has a line width of at most 25 microns.
 9. Themicroarray of claim 1, wherein said solar cells have respective activesurfaces facing away from said substrate, each solar cell in a setcomprising:a semiconductor base layer on said isolation layer; asemiconductor emitter layer on said base layer, an interface betweensaid base and emitter layers forming a p/n junction; a base contact onthe active surface, said base contact extending through said emitterlayer to said base layer; an emitter contact on the active surface andin electrical communication with said emitter layer, said p/n junctionestablishing a cell voltage and a cell current between said base andemitter contacts in response to incident light on the cell's activesurface; and an interconnect on said active surface formed integrallywith one of said base and emitter contacts and in contact with one ofsaid base and emitter contacts on another one of said solar cells insaid set, the interconnects configuring the solar cells to sum theircell voltages and currents to supply a set voltage and a set current atan output.
 10. The microarray of claim 9, wherein said solar cells' p/njunctions have respective active areas that are scaled so that theirrespective cell currents supply the set current, said interconnectsbeing configured to connect the solar cells exclusively in series to sumtheir voltage to produce the set voltage.
 11. The microarray of claim 9,wherein said isolation layer has a conductivity opposite to saidsubstrate and said base layer.
 12. The microarray of claim 9, whereinsaid interconnect has a line width of at most 25 microns.
 13. Themicroarray of claim 1, wherein said substrate is single-crystal silicon(Si) and said solar cells are gallium-arsenide (GaAs).
 14. Themicroarray of claim 13, wherein said isolation layer comprises a III-Vmaterial whose band gap exceeds that of silicon.
 15. The microarray ofclaim 14, wherein said III-V material comprises a GaAs compound.
 16. Themicroarray of claim 1, wherein said solar cells are multi-function solarcells having active surfaces facing away from said substrate, eachmulti-junction solar cell comprising a plurality of base-emitter layerpairs;a base contact on the active surface that extends through theplurality of base-emitter pairs to the base layer on said isolationlayer; and an integral emitter contact/interconnect on the activesurface in electrical communication with the topmost emitter layer andwith said base contact on another one of said multi-junction solar cellsin said set, said base-emitter layer pairs having successively largerband gap energies so that light incident on the microarray's activesurface penetrates all of said base-emitter layer pairs to produce apotential between said base and integral emitter contacts that isapproximately the sum of the potentials produced by the differentbase-emitter layer pairs.
 17. The microarray of claim 16, wherein saidsubstrate is single-crystal germanium.
 18. A monolithically integratedsolar cell microarray that supplies an output voltage and an outputcurrent at a terminal in response to irradiation of light on its activesurface, comprising:a monolithic single-crystal germanium substratehaving a band gap of approximately 0.6 electron volts (ev); an isolationlayer on said substrate; a gallium-arsenide (GaAs) base layer on saidisolation layer; a gallium-arsenide (GaAs) emitter layer formed on topof said base layer; a trench in said base and emitter layers thatexposes said isolation layer and defines a plurality of solar cells thateach produce a cell voltage and which are scaled to provide the arraycurrent, said isolation layer having lattice properties that arecompatible with those of the single-crystal germanium substrate and theGaAs base layer and having a band gap greater than 0.6 ev that isolatesthe solar cells from the germanium substrate and from each other; aplurality of base contacts on the active surface, said base contactsextending through said emitter layer to said base layer in therespective solar cells; and a plurality of integral emittercontact/interconnects on the active surface in electrical communicationwith said emitter layer in the respective solar cells and with said basecontacts on successive ones of said solar cells so that said solar cellsare connected in series to sum their cell voltages to produce the arrayvoltage and array current at the terminal.
 19. The microarray of claim18, wherein said isolation layer comprises a gallium-arsenide (GaAs)compound whose band gap exceeds 1.6 ev.
 20. The microarray of claim 18,wherein said solar cells have a non-rectangular shape.
 21. Themicroarray of claim 18, wherein said isolation layer has a conductivityopposite to said substrate and said base layer.
 22. The microarray ofclaim 18, wherein said emitter contact/interconnect has a line width ofat most 25 microns.
 23. A method of fabricating a monolithicallyintegrated solar cell microarray, comprising:providing a monolithicsingle-crystal semiconductor substrate; epitaxially forming an isolationlayer on said substrate, said isolation layer having lattice propertiesthat are compatible with those of the single-crystal semiconductorsubstrate, epitaxially forming a semiconductor base layer on saidisolation layer; epitaxially forming a semiconductor emitter layer onsaid base layer, said base and emitter layers comprising III-V materialsand an interface between them forming a p/n junction; and patterningsaid base and emitter layers to expose said isolation layer and therebydefine an array of discrete solar cells on said monolithicsingle-crystal substrate that produce respective cell voltages and cellcurrents in response to irradiation of light on said microarray, saidisolation layer having a band gap that electrically isolates the solarcells from the semiconductor substrate and from each other.
 24. Themethod of claim 23, wherein patterning said base and emitter layerscomprises:forming a photoresist mask on said emitter layer to expose atrench pattern; etching the exposed trench pattern into the emitterlayer and the underlying portion of the base layer to expose theisolation layer; and removing the photoresist mask.
 25. The method ofclaim 24, wherein said photoresist mask defines non-rectangular shapedsolar cells.
 26. The method of claim 23, wherein the solar cells' p/njunctions have respective active areas, said solar cells' base andemitter layers being patterned to scale the p/n junction active areas sothat their cell currents supply a selected array current.
 27. The methodof claim 26, further comprising:patterning said emitter and base layersto form a base contact region for each of said solar cells; forming anemitter contact pad on said emitter layer for each of said solar cells;and forming a metallization pattern that is affixed to the base contactregions and emitter contact pads to connect a selected number of saidsolar cells in series to sum their cell voltages to produce an arrayvoltage along with said array current at an output terminal.
 28. Themethod of claim 27, wherein forming the metallization patterncomprises:forming a base contact in each of said base contact regions;and forming an integral emitter contact/interconnect on each of saidemitter contact pads to one of said base contacts on another one of theselected solar cells.
 29. The method of claim 28, wherein said basecontact and said emitter contact/interconnect are formed usingphotolithographic liftoff processes.
 30. The method of claim 23, furthercomprising:patterning said emitter and base layers to form a basecontact region for each of said solar cells; forming an emitter contactpad on said emitter layer for each of said solar cells; forming a basecontact in each of said base contact regions; forming an emitter contacton each of said emitter contact pads; and forming an interconnectintegrally with one of said base and emitter contacts and in contactwith one of said base and emitter contacts on another one of theselected solar cells to configure said solar cells to sum their cellvoltages and currents to produce an array voltage and a selected arraycurrent at an output terminal.
 31. The method of claim 30, wherein thesolar cells' p/n junctions have respective active areas, said solarcells' base and emitter layers being patterned to scale their activeareas with respect to a reference area so that their cell currentssupply the selected array current.
 32. The method of claim 31, whereinsaid interconnects are formed integrally with respective ones of saidemitter contacts in a single parallel photolithographic liftoff step tocontact the base contacts on another one of said solar cells to connectthem in series to produce the array voltage at said terminal.
 33. Themethod of claim 23, wherein said substrate is single-crystal germanium.34. The method of claim 33, wherein said germanium substrate has a bandgap of approximately 0.6 ev, said isolation layer comprising a III-Vmaterial whose band gap isolates the solar cells from the substrate. 35.The method of claim 23, wherein said substrate is single-crystal silicon(Si) and said solar cells are gallium-arsenide (GaAs).
 36. The method ofclaim 35, wherein said isolation layer comprises a III-V material whoseband gap exceeds that of silicon.
 37. The method of claim 23, whereinsaid solar cells are multi-junction solar cells that comprise aplurality of base-emitter layer pairs that are formed on the substratewith the bottommost base layer being formed on the isolation layer andthe topmost layer having an active surface that faces away from saidsubstrate, further comprisingforming a base contact on the activesurface that extends through the plurality of base-emitter layer pairsto the base layer on said isolation layer; and forming an integralemitter contact/interconnect on the active surface in electricalcommunication with the topmost emitter layer and with said base contacton another one of said multi-junction solar cells in said set, saidbase-emitter layer pairs having successively larger band gap energies sothat light incident on the microarray's active surface penetrates all ofsaid base-emitter layer pairs to produce a potential between said baseand integral emitter contacts that is approximately the sum of thepotentials produced by the different base-emitter layer pairs.
 38. Amethod of fabricating a monolithically integrated solar cell microarray,comprising:providing a monolithic single-crystal germanium substratehaving a band gap of approximately 0.6 electron volts (ev); epitaxiallyforming an isolation layer comprising a III-V material on saidsubstrate; epitaxially forming a base layer comprising a III-V materialon said isolation layer; epitaxially forming an emitter layer comprisinga III-V material on said base layer, an interface between said base andemitter layers forming a p/n junction; and patterning said base andemitter layers to expose said isolation layer and thereby define anarray of discrete solar cells on said monolithic single-crystalgermanium substrate that produce respective cell voltages and cellcurrents in response to irradiation of light on said microarray, saidisolation layer having lattice properties that are compatible with thoseof the single-crystal germanium substrate and the base layer and havinga band gap greater than 0.6 ev that isolates the solar cells from thegermanium substrate and from each other.
 39. The method of claim 38,wherein the III-V material in said base and emitter layers comprisegallium-arsenide.